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LeadSoc Technologies Pvt. Ltd. Verified employer
Actively hiring · Posted 1mo ago · JEV260985F36B528A
Perform full-chip and block-level Static Timing Analysis (STA)Setup and analyze timing constraints (SDC) including clocks, I/O constraints, exceptionsPerform timing closure for different modes and corners (MCMM)Identify and debug setup, hold, recovery, and removal violations Handle ECOs related to timing fixes